Tell an engineer they can't have the fancy new tools, and they'll either give up or get dangerously creative. Huawei, it seems, chose violence. Locked out of the cutting-edge machines that print the world's best chips, the company decided to just stack its circuits like a tiny silicon lasagna.

Folding Circuits Into the Third Dimension

Huawei's answer to U.S. export controls is an architecture it calls "LogicFolding," which folds traditional flat 2D circuit layouts into vertical 3D stacks. By shortening the physical paths signals travel, the design reduces resistance and capacitance on critical wiring — and Huawei claims it delivers a 53.5% density increase and a 41% efficiency boost over its previous 2D designs.

The technique is set to debut in the Kirin 2026 smartphone processor this autumn, with plans to extend it to the company's Ascend AI chips down the road. Notably, a Chinese university has reportedly built a 3D chip-design tool tailored specifically to the LogicFolding approach.

The Sanctions That Backfired

Here's the kicker. Without access to the extreme ultraviolet (EUV) lithography machines restricted by Washington, Huawei is aiming for transistor density equivalent to a 1.4nm process by 2031 — the long way around. The company's rotating chairman even thanked the U.S., saying Huawei wouldn't have pushed this hard without the pressure.

That quote is the whole story in a sentence. Export controls were meant to freeze a rival in place; instead they may have lit a fire under a domestic engineering effort that now has no choice but to innovate. Necessity isn't just the mother of invention — sometimes it's the mother of an entire semiconductor roadmap.

Whether LogicFolding lives up to the spec sheet is a 2026 question we'll get to test soon. But "we built a workaround and sent a thank-you note" is one of the boldest flexes in chip history.

Source: Tom's Hardware